Job Summary
T Floorplanning and power planning Placement, CTS, routing, and physical verification Timing closure and congestion optimization IR drop, EM, and signal integrity analysis ECO implementation and signoff closure Coordinate with STA, DFT, RTL, and package teams
Key Responsibilities
ASIC backend flow understanding STA concepts and timing analysis Tools: ICC2, Innovus, PrimeTime, Tempus Physical verification: DRC/LVS/ERC Scripting: TCL/Python/Shell
Skill Requirements
Advanced node experience (7nm/5nm/3nm) Low-power implementation Multi-voltage and clock-domain design
Other Requirements
1. Certification In Advanced Physical Design Techniques Is Optional But Valuable.
2. Certification In Relevant Industry Standards (E.G., Ieee, Iso) Is A Plus.
Information at a Glance